The invention relates to an integrated circuit, more particularly but not exclusively to a charge-coupled device comprising a clock voltage generator circuit having a number of clock lines for receiving and transferring clock voltages which have a reference level and an active level, each clock line being connected to the output of a first inverter circuit, whose input is connected to means for applying a pulse voltage, while each clock line is connected to a switch in the form of an insulated gate field effect transistor (designated hereinafter as a clamping transistor), which is open when the clock line is at the active level and which, when the clock voltage is at the reference level, forms a low-impedance connection between the clock line and a point which is also at the reference level. Such a circuit arrangement is known inter alia from U.S. Pat. No. 4,230,951.
Charge-coupled devices are devices in which a pattern of potential wells and potential barriers is induced at or near the surface of a semiconductor body by means of clock voltages which are applied to a series of clock electrodes located above the surface. Information can be stored and transported in the device in the form of discrete packets of electrical charge which are stored in the potential wells and are mutually insulated by the potential barriers. The information can be displaced by applying a clock electrode, below which no information is stored, to the active voltage level, as a result of which a deeper potential well is generated below this clock electrode than below an adjacent clock electrode which remains at the reference level and below which charge is stored. This charge can flow into the deeper potential well below the first-mentioned clock electrode. The clock voltages are supplied to the clock electrodes via the clock lines, which are alternately connected to one of the clock electrodes.
At the instant at which the first-mentioned electrode is applied to the active voltage level, the voltage at the adjacent electrode can vary due to capacitive coupling. As a result, the potential profile below the adjacent clock electrode can change so that distortion of the information stored below the adjacent clock electrode can occur. More particularly, it is then possible that the voltage at the preceding electrode deviates to such an extent from the reference level that the potential well below this clock electrode also becomes much deeper and attracts charge of the charge packet stored below the preceding electrode. The voltage at the succeeding electrode may also deviate to such an extent that the potential well below this electrode becomes much less deep and charge flows from below this electrode to below the succeeding electrode.
In types of integrated circuits other than the charge-coupled devices described herein, such as in, for example, memories, such noise problems due to cross-talk between the clock lines or between the elements controlled by the clock lines may also arise.
FIG. 5 of U.S. Pat. No. 4,230,951 indicates a method of solving the problem of clock cross-talk in that by means of switches the clock lines, which are at the reference level, are clamped via a low impedance at the reference level at the instant at which the cross-talk is expected. In the known device described, for this purpose, in the case of n clock lines, each clock line is connected via (n-1) clamping transistors to a common point at the reference level, these (n-1) clamping transistors each being controlled by one of the (n-1) remaining clock lines. The clamping transistor, whose gate is connected to the clock line applied to the active level, becomes conducting and clamps the associated clock line and hence the clock electrodes controlled by this clock line at the reference level. The remaining (n-2) clamping transistors connected to this clock line remain non-conducting. This known device has the disadvantage that each clock line requires several clamping transistors. In general these clamping transistors occupy much space because of the requirements imposed on the low-ohmic character in the conductive state.